
Micrel, Inc.
KSZ8841-PMQL
October 2007
56
M9999-100407-1.5
PHY 1 MII Register Basic Status Register (Offset 0x04D2): P1MBSR
This register contains the MII register control for the chip function.
Bit
Default
R/W
Description
Is the Same as
15
0
RO
T4 capable
1 = 100 Base-T4 capable
0 = Not 100 BaseT4 capable
14
1
RO
100 Full capable
1 = 100BaseTX full duplex capable
0 = Not 100BaseTX full duplex capable
Always 1
13
1
RO
100 Half capable
1 = 100BaseTX half duplex capable
0 = Not 100BaseTX half duplex capable
Always 1
12
1
RO
10 Full capable
1 = 10BaseT full duplex capable
0 = Not 10BaseT full duplex capable
Always 1
11
1
RO
10 Half capable
1 = 10BaseT half duplex capable
0 = Not 10BaseT half duplex capable
Always 1
10-7
0
RO
Reserved
6
0
RO
Preamble suppressed
NOT SUPPORTED
5
0
RO
AN complete
1 = Auto-negotiation complete
0 = Auto-negotiation not completed
P1SR, bit 6
4
0
RO
Far end fault
1 = Far end fault detected
0 = No far end fault detected
P1SR, bit 8
3
1
RO
AN capable
1 = Auto-negotiation capable
0 = Not auto-negotiation capable
P1CR4, bit 7
2
0
RO
Link status
1 = Link is up
0 = Link is down
P1SR, bit 5
1
0
RO
Reserved
0
RO
Extended capable
1 = Extended register capable
0 = Not extended register capable
PHY 1 PHYID Low Register (Offset 0x04D4): PHY1ILR
This register contains the PHY ID (low) for the chip function.
Bit
Default
R/W
Description
15-0
0x1430
RO
PHYID low
Low order PHYID bits